The present invention generally relates to semiconductor memory devices, and more particularly to a static random access memory (SRAM) in which a memory cell occupies a small area in a plan view of the memory cell.
Presently, there are demands to further improve the integration density of semiconductor memory devices. In the case of the SRAM, however, it is difficult to satisfy such demands due to the large number of transistors used in the SRAM. Accordingly, there is a need to reduce the number of transistors and arrange elements of the SRAM at locations such that the further improvement of the integration density becomes possible.
FIG. 1 shows an essential part of a conventional SRAM. A memory cell part of the SRAM shown in FIG. 1 includes transistors Q1 and Q2 for holding data, load resistors R1 and R2, transistors Q3 and Q4 which are used as transfer gates, a sense amplifier SA, bit lines BL and BL, and a word line WL. V.sub.DD denotes a positive power source voltage and V.sub.SS denotes a negative power source voltage. This SRAM thus uses four transistors and two resistors.
On the other hand, there is a known SRAM which uses transistors in place of the load resistors R1 and R2 in FIG. 1. Hence, this known SRAM uses six transistors.
Furthermore, there is another known SRAM which is designed to reduce both power consumption and noise. This other known SRAM uses two complementary metal oxide semiconductor (CMOS) inverters which respectively have an n-channel transistor and a p-channel transistor, and two transistors.
The SRAMs of the types described above use the bit line pair BL and BL, and thus, it is possible to omit one of the bit line pair BL and BL and accordingly omit one transistor which functions as the transfer gate.
Compared to a dynamic random access memory (DRAM), however, the SRAMs described above use a large number of transistor per memory cell. For this reason, it is difficult to reduce the area occupied by the SRAM in the plan view.
If some sacrifices are made, it is possible to realize a memory cell made up of three transistors and two resistors, and a memory cell made up of two CMOS inverters and one transistor. However, up to the present, there has not been proposed a practical memory cell which is made up of two transistors or made up of two CMOS inverters.